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wireless components wideband - receiver pmb 2408 v1.1 data sheet march 2000
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 2 22.03.00 contents 0 revision history 3 1 general overview 4 1.1 features 4 1.2 applications 4 1.3 functional description 4 2 pinning 5 2.1 pin description 5 2.2 pin configuration 6 2.3 package outline 6 3 functional block diagram 7 4 circuit description 8 5 internal input/output circuits 12 6 electrical characteristics 14 6.1 absolut maximum ratings 14 6.2 operational range 15 6.3 ac/dc characteristics 16 7 test circuits 25 7.1 test circuit 1 25 7.2 test circuit 1.1 26 7.3 test circuit 1.2 26 7.4 test circuit 2 27 7.5 test board 28 8 design hints 8.1 lna matching for 925 mhz 35 8.2 vco: possibility of i/q phase error correction 36 8.3 sample and hold: offset compensation diagram for smallband applications 37 8.4 sample and hold: offset compensation diagram for wideband applications 38 9diagrams 39
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 3 22.03.00 0 revision history data sheet 5/99 data sheet ...... # subjekt page item page item change
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 4 22.03.00 1 general overview 1.1 features - heterodyne receiver with demodulator - on-chip low noise amplifier (lna), gain switchable - switchable (on / off) reference voltage for biasing either the internal lna or an external lna - demodulation and generation of i/q components - low mixer noise 9db (ssb) - high input intercept point +2db - integrated phase shifter - if amplifier with 80db programmable gain control (pgc) in steps of 2db - active part of a local-oscillator (lo2) with external tuning circuit or possibility to use it as amplifier - two differential operational amplifiers for use as base-band amplifier in smallband applications - low power consumption due to highly flexible power down capability - wide input frequency range up to 2.5 ghz - wide if range from 40 mhz to 460 mhz - channel bandwidth (baseband bandwidth) up to 5 mhz (vs = 2.7v) - low supply voltage down to 2.7v - p-tqfp-48 package - temperature range -40 to 85c 1.2 applications - vector modulated digital mobile cellular systems as wlan etc. - various demodulation schemes, such as pm, psk, fsk, qam, qpsk, gmsk - space and power saving optimisations of existing discrete demodulator circuits 1.3 functional description the pmb 2408 is a single-chip double-conversion heterodyne receiver with lo-phase shifting circuitry for the i/q-phase demodulation on chip. it also includes a low noise amplifier with switchable gain, a switchable reference voltage for biasing either the internal or an external lna, the second local oscillator with a vco output buffer, a programmable gain controlled if amplifier, two differential operational amplifiers for base band purposes in smallband applications, and a power down circuitry. the pmb 2408 is designed for vector modulated digital systems like wlan with larger channel bandwidth.
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 5 22.03.00 2 pinning 2.1 pin description pin no. symbol function 1 vs2 supply voltage 2 (if circuit part, op. amp, 3-wire bus, offset compensation) 2 div1/3 divider-logic input 3, 6, 16, 22, 30 gnd ground 4 csh1 sample and hold capacitance 1 5 csh2 sample and hold capacitance 2 7 oce sample and hold input 8 ifi non-inverting if input 9 ifix inverting if input 10 sygcdt data input ( 3 wire bus of pgc ) 11 sygccl clock input ( 3 wire bus of pgc ) 12 pgcstr enable input ( 3 wire bus of pgc ) 13 six inverted signal input of first mixer 14 si non-inverted signal input of first mixer 15 rxon1 power down input 1 ( rf ) 17 lo1x inverting input for first local oscillator 18 lo1 non-inverting input for first local oscillator 19 vs1 supply voltage 1 ( first mixer, bias for lna ) 20 mo non-inverted output of first mixer 21 mox inverted output of first mixer 23 lo2ox inverted vco output buffer 24 lo2o non-inverted vco output buffer 25 gnd3 ground3 ( lna ground ) 26 ao lna output 27 vs3 supply voltage 3 ( lna ) 28 aref lna reference input 29 ai lna input 31 puplo2 power up input for vco and vco output buffer 32 lo2x base inverting input for second local oscillator 33 lo2ex emitter inverting input for second local oscillator 34 lo2e emitter non-inverting input for second local oscillator 35 lo2 base non-inverting input for second local oscillator 36 rxon2 power down input 2 for the if-part and op. amp.'s 37 soqx inverting quadratur demodulator signal output 38 fbq feedback tap for ?fixed-gain? op.-amp.?s (q) 39 qrx inverting op. amp. signal output (q) 40 qr non-inverting op. amp. signal output (q) 41 fbqx feedback tap for ?fixed-gain? op.-amp.?s (q) 42 soq non-inverting quadratur demodulator signal output 43 soix inverting in-phase demodulator signal output 44 fbi feedback tap for ?fixed-gain? op.-amp.?s (i) 45 irx inverting op. amp. signal output (i) 46 ir non-inverting op. amp. signal output (i) 47 fbix feedback tap for ?fixed-gain? op.-amp.?s (i) 48 soi non-inverting in-phase demodulator signal output
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 6 22.03.00 2.2 pin configuration (top view) 1 48 2.3 package outline quad flat package p-tqfp-48
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 7 22.03.00 3 functional block diagram
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 8 22.03.00 4 circuit description the input signal is amplified by the internal or an external lna and filtered in an external filter (lna programming see table3). the filtered signal si/six and the first local oscillator signal lo1/lo1x are mixed down to an intermediate frequency (if). the open collector output of the mixer generates a differential current at pins mo/mox which is filtered by an external lc tank circuit. an external saw filter following this lc circuit is used for channel selection. the amplification of the if signal is performed by a digitally programmable gain-controlled amplifier. gain programming is done by loading a 16 bit control word into a register via the 3 - wire bus (see fig. 1 and 3 and also table 3 and 4). serial data is clocked out from msb to lsb. after power-down the information in the register is lost. the second local oscillator signal lo2 is generated either by the active part of an on-chip oscillator (with external tuning circuit) or by an external vco. depending on the logic level at pin div1/3 (see table 2), the internal lo2 signal is fed directly to the buffered output (div1/3: l) or to a divider by 3 (div1/3: h) and then to a buffered output and also to a divider, which generates orthogonal signals at half the vco frequency. the filtered if signal re-enters the chip at the ifi/ifix input, where it is amplified and converted to the final output frequency with each of the orthogonal signals. the resulting in-phase and quadrature signals pass through differential output drivers and appear at soi/soix and soq/soqx outputs, respectively. two differential operational amplifiers with the input signals ini/inix (inq/inqx) and the output signals ir/irx (qr/qrx) can be used as baseband amplifiers or active baseband filters in smallband applications (see design hint 8.3 page 37). at both outputs ir/irx (qr/qrx) the differential offset is sensed via the sample and hold circuitry. a feedback loop corrects the remaining offset error below the tolerable input value of the baseband a/d converter. for wideband applications please refer to design hint 8.4 page 38. differential signals and symmetrical circuitry are used throughout. bias drivers generate internal temperature- and supply voltage compensated reference voltages required by various circuit blocks. switching the power down inputs rxon1,rxon2 and puplo2 from high to low (see table 1 and fig. 2.1) sets the circuit from its normal operating mode into a mode with reduced supply current. fig. 2.2 shows the supply function. there are three supply voltages: vs1 supplies the first mixer and the standby rf circuit, vs2 supplies the complete if part and vs3 supplies the lna. the lna has an own ground pin gnd3, the rest of the circuits are grounded by gnd. figure 1: block diagram of pgc and 3 - wire bus 9db... ...-5db 9db... ...-5db 9db... ...-5db 9db... ...-5db 24db 0db 3 - wire bus / decoder pgcstr sygcdt sygccl lna stage 1 bit bit bit bit bit bit bit bit 1 23 4 5 6 8 1011121314 15 16 9 7 no function ifi/ stage 2 stage 3 stage 4 stage 5 i/q-demodulator 10db soq/soqx soi/soix ifix lsb msb
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 9 22.03.00 figure 2: power down- and supply-function figure 2.1: power down function figure 2.2: supply function
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 10 22.03.00 figure 3: three-wire bus timing diagram loading of data signal with positive clocke edges t table 1: power down function rxon1 rf part rxon2 if part & op.amp.'s puplo2 vco/buffer div. by 1 or 3 l off l off l off hon h on h on the pgc adjustment is not stored during power down of rxon2. table 2: divider div1/3: switch logic div 1/3 divider l%1 h%3 table 3: lna gain control: general reference voltage gain control bit 14 reference switch bit 15 gain switch aref = on h-gain 1 1 aref = on l-gain 1 0 aref = off 0 x as lna as switch bit 14 bit15 bit 14 bit 15 h-gain 11aref=on1 1 l-gain 10aref=off0 1
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 11 22.03.00 table 4: table of pgc-, lna-gain control bit pgc lna no g/db st. 1 stage 2 stage 3 stage 4 stage 5 aref gain func- tion pgc 12345678910111213141516 70 1111111111111xxx 68 1110111111111xxx 66 1101111111111xxx 64 1100111111111xxx 62 1011111111111xxx 60 1010111111111xxx 58 1001111111111xxx 56 1000111111111xxx 54 1000110111111xxx 52 1000101111111xxx 50 1000100111111xxx 48 1000011111111xxx 46 1000010111111xxx 44 1000001111111xxx 42 1000000111111xxx 40 0100111111111xxx 38 0011111111111xxx 36 0010111111111xxx 34 0001111111111xxx 32 0000111111111xxx 30 0000110111111xxx 28 0000101111111xxx 26 0000100111111xxx 24 0000011111111xxx 22 0000010111111xxx 20 0000001111111xxx 18 0000000111111xxx 16 0000000110111xxx 14 0000000101111xxx 12 0000000100111xxx 10 0000000011111xxx 8 0000000010111xxx 6 0000000001111xxx 4 0000000000111xxx 2 0000000000110xxx 0 0000000000101xxx -2 0000000000100xxx -4 0000000000011xxx -6 0000000000010xxx -8 0000000000001xxx -10 0000000000000xxx g/db bit lna 12345678910111213141516 15 xxxxxxxxxxxxx 1 1 x -5 xxxxxxxxxxxxx 1 0 x 1 = high, 0 = low, x = don't care
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 12 22.03.00 5 internal input/output circuits internal i/o circuits from pin 1 to 12 and 37 to 48
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 13 22.03.00 internal i/o circuits from pin 13 to 36
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 14 22.03.00 6 electrical characteristics 6.1 absolute maximum ratings the maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the ic will result. ambient temperature t a = -40 to 85c # parameter symbol limit values unit remarks min. max. 1 supply voltage v s -0.3 5.5 v 2 input/output voltage output voltage aref v io -0.3 0 vs + 0.3 2.5 v except lna 3 open collector output voltage mo,mox ao v oc 1.7 1.0 vs + 0.3 vs + 0.3 v 4 lna input voltage v ai -3 v rxon1=l 5 lna input current i ai 10 ma rxon1=l 6 differential input voltage (any differential input) v i 2vpp 7 junction temperature t j 125 c 8 storage temperature t s -55 125 c 9 thermal resistance (junction to ambient) r thja 165 k/w 10 esd-integrity v esd 1000 1000 v according mil-std 883d, method 3015.7 the rf pins 20, 21, 26, 29, 32, 33, 34 and 35 are not protected against voltage stress > 300v (versus vs or gnd). the high frequency performance prohibits the use of adequate protective structures.
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 15 22.03.00 6.2 operational range within the operational range the ic operates as described in the circuit description. the ac/dc characteristics limits are not guaranteed. supply voltage v s = 2.7v to 4.5v; ambient temperature t a = -40 to 85c; refer to test circuit 1. # parameter symbol limit values unit remarks min. max. lna 1 ai input frequency f si 2500 mhz first mixer 2 si/six input level p si -11 dbm 3 si/six input frequency f si 2500 mhz 4 lo1/lo1x input level p lo1 -11 3 dbm 5 lo1/lo1x input frequency f lo1 2500 mhz if amplifier (pgc) 6 intermediate frequency if 40 460 mhz 7 ifi/ifix input level p ifi -12 dbm 8 ifi/ifix input frequency f ifi 40 460 mhz vco (second local oscillator) 9lo2 input level p lo2 -35 0 dbm 10 lo2 input frequency f lo2 80 920 mhz vco as amplifier 11 vco frequency range f vco 80 920 mhz 12 lo2o output level p lo2o 4dbm tuned for reso-nance, measured with high impedance probe 13 lo2o output frequency f lo2o 80 26.7 920 307 mhz mhz div1/3: l div1/3: h demodulator outputs 14 ir/x,qr/x outp. bandw. b out 0 9.5 mhz 3db roll off, see ac/dc characteristics page 21 power down and logic inputs 15 sygcdt/sygccl/pgcstr/ rxon1/rxon2/puplo2/oce input voltage-l v l 00.5v 16 sygcdt/sygccl/pgcstr/ rxon1/rxon2/puplo2/oce input voltage-h v h 2.0 vs v 17 input capacitance c i 2pf note: power levels are referred to impedance of 50 ohms
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 16 22.03.00 6.3 ac/dc characteristics ac/dc characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. typical characteristics are the median of the production. supply voltage v s = 2.7v to 4.5v; ambient temperature t a = 25c # parameter symbol limit values unit test condition test min. typ. max. circuit supply currents 1 supply current i s 7.8 8.4 16 32.5 10.5 11.3 20 42 10 13.13 14.1 24 51.3 a ma ma ma ma rxon1/rxon2/puplo2 l / l / l h / l / l l / l / h l / h / l h / h / h lna input signal ai 2 input impedance see diagrams 9.1 and 9.2, pages 42-44 2b 3max. input level p ai -23 -16 -20 -13 dbm 1db compr. at ao, h, l gain 900mhz h, l gain 1.8/1.9ghz 1 4 input intercept point ipip3 -7/-5/-5 -7/-5/-5 -4/-2/-2 -4/-2/-2 -1/+1/+1 -1/+1/+1 dbm h gain, 0.9/1.8/1.9ghz l gain, 0.9/1.8/1.9ghz 1 5 noise figure (values with matching for 900 mhz see design hints 9.1, page 39) n ai n ai n ai n ai 1.5 3 8 9 2.5 3.5 9 10 db db db db f rf =900mhz;h gain f rf = 1.8/1.9ghz ;h gain f rf = 900mhz ;l gain f rf = 1.8/1.9ghz ;l gain 1 5.1 temp. coefficient t c 0.006 db/k see appl. circuit page 35 output signal ao 6 output impedance see diagrams 9.1 and 9.2, pages 42-44 2b 7 output collector current i ao 5 0.5 ma ma h gain l gain 8 gain from signal input without matching. g lna 15 -5 10.5 -9.5 17 -3 13.5 -6.5 19 -1 16.5 -3.5 db db db db f rf =900mhz, h gain l gain f rf =1.8/1.9ghz, h gain l gain 1 8.1 temp. coefficient t c -0.01 db/k see appl. circuit page 35 9 gain step ? g 19 20 21 db
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 17 22.03.00 ac/dc characteristics (cont'd) supply voltage v s = 2.7v to 4.5v; ambient temperature t a = 25c # parameter symbol limit values unit test condition test min. typ. max. circuit first mixer input si/six 10 input impedance see diagram 9.3, page 45 2a 11 max. input level p si -14 -10 -11 -7 dbm 1db compr. at mo/x f si =900mhz f si =1.8/1.9ghz 1 12 input intercept point 3rd order p ipi3 2 -3 dbm f si =900mhz f si =1.8/1.9ghz 1 13 blocking level ? f = 3 mhz p b -11 -7 -8 -4 dbm 3db attenuation of wanted signal at mo/mox f si =900mhz f si =1.8/1.9ghz 1 14 input frequency f si 2500 mhz 1 15 noise figure n si n si 6/6.5 10/10.5 9/9.5 13/13.5 db db db db if = 246/336 mhz dsb noise, f c =900mhz dsb noise, f c = 1.8/1.9ghz ssb noise, f c =900mhz ssb noise, f c = 1.8/1.9ghz see diagrams 2, 4, page 39 1 15.1 temp. coefficient t c 0.01 db/k output mo/mox (open collector) 16 output impedance see diagram 9.5, page 47 2c 17 total output collector current i mo+mox 4ma 1 18 power gain from signal input g mo 11 7 5 2 14 10 8 4 17 13 11 6 db db db db f mo =40mhz, f rf =900mhz f mo =40mhz, f rf =1.8/1.9ghz f mo =246mhz, f si =900mhz, * f mo =246mhz, f si =1.8/1.9ghz, * see diagram 3, page 39 1 1 18.1 temp. coefficient t c -0.015 db/k 19 output frequency if f if 40 246 460 mhz 1 * tank circuit at mo/mox matched to output / tuned for resonance
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 18 22.03.00 ac/dc characteristics (cont'd) supply voltage v s = 2.7v to 4.5v; ambient temperature t a = 25c # parameter symbol limit values unit test condition test min. typ. max. circuit input lo1/lo1x (first mixer local oscillator) 20 input impedance see diagram 9.4, page 46 2a 21 input level p lo1 v lo1 -11 177 3 890 dbm mvpp see diagram 1, page 39 1 1 22 input frequency f lo1 2500 mhz 1 isolation of first mixer 23 from si to mo a si-mo 30 db f si =945mhz; f lo1 =900mhz 1 24 si to lo1 a si-lo1 60 db " 1 25 lo1 to mo a lo1- mo 50 db " 1 26 lo1 to si a lo1-si 60 db " 1 27 mo to si a mo-si 50 db " 1 28 mo to lo1 a mo- lo1 65 db " 1 29 from si to mo a si-mo 24 db f si =1.845ghz; f lo1 =1.8ghz 1 30 si to lo1 a si-lo1 54 db " 1 31 lo1 to mo a lo1- mo 44 db " 1 32 lo1 to si a lo1-si 54 db " 1 33 mo to si a mo-si 44 db " 1 34 mo to lo1 a mo- lo1 59 db " 1 isolation between first mixer output to if input 35 from mo to ifi a mo-ifi 60 db if = 40 .... 460 mhz 1 isolation between lna output to first mixer input 36 from ao to si a ao-si 45 db f rf =900 mhz 1 37 from ao to si a ao-si 45 db f rf =1.8/1.9ghz 1
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 19 22.03.00 ac/dc characteristics (cont'd) supply voltage v s = 2.7v to 4.5v; ambient temperature t a = 25c # parameter symbol limit values unit test condition test min. typ. max. circuit if amplifier (pgc) input ifi/ifix 38 input impedance see diagram 9.6, page 48 2a 39 max. input level p ifi v ifi -12 155 dbm mvpp 1db compr. pgc gain: -10db see diagram 5.1, page 39 1 1 40 input intercept point p ipi see diagram 5.1, page 39 1 41 input frequency f si 40 246 460 mhz 1 42 noise figure n si 6 7 db pgc gain: 70db see diagram 5.1, page 39 1 vco (second local oscillator lo2) input lo2/lo2x (when used as amplifier for an external vco) 43 input impedance see diagram 9.7, page 49 2b 44 input level p lo2 v lo2 -20 63 0 630 dbm mvpp into 50 ohms application hint 1 1 45 input frequency f lo2 80 920 mhz 1 voltage controlled oscillator vco (lo2) 46 vco frequency range f vco 80 492 920 mhz * 1.1 47 vco tuning range ? f vco 32 mhz vt = 0.6 ... 2.3v ** 1.1 * depending on external tuning circuit ** test circuit 1.1 (f vco = 492mhz), page 26 and page 36
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 20 22.03.00 ac/dc characteristics (cont'd) supply voltage v s = 2.7v to 4.5v; ambient temperature t a = 25c # parameter symbol limit values unit test condition test min. typ. max. circuit output lo2o/lo2ox 48 output resistance (diff.) r lo2o 1kohms 49 output capacitance (diff.) c lo2o 1 pf parallel to r lo2o 50 output level p lo2o -15 dbm tuned for resonance 1 51 output level p lo2o 4 dbm tuned for resonance, measured with high impedance probe (differential) 52 output frequency f lo2o 80 492 920 mhz div1/3: l 53 output frequency f lo2o 26.7 164 307 mhz div1/3: h 54 ssb noise referenced l(fm) -121 -126 -131 dbc/hz fm=600 khz fm=1.8 mhz fm=6 mhz; using high q coil, q=60-70 for oscillator tank circuit. ** 1.1 55 power on delay t po 0.3 s ** test circuit 1.1 (f vco = 492mhz), page 26 and page 36
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 21 22.03.00 ac/dc characteristics (cont'd) supply voltage v s = 2.7v to 4.5v; ambient temperature t a = 25c # parameter symbol limit values unit test condition test min. typ. max. circuit if and bb chain: pgc==>demodulator outputs soi/soix, soq/soqx 56 output resistance (diff.) r out 75 ohms 57 output capacitance (diff.) c out 1pf 58 frequency roll off f out 3.0 3.6 4.1 5.0 6.0 6.8 7.0 8.4 9.5 mhz mhz mhz vcc = 2.7v vcc = 3.6v vcc = 4.5v see diagram 6 page 41 and design hint 9.4 page 38 59 dc output level v outdc 0.95 v 1 60 diff. output offset voltage v so/x 30 100 mv without offset comp. oce = low 1 61 ac voltage swing (diff.) v outac 2.5 vpp differential 1 62 voltage gain from if to i/q-bb output (if: 225 / 246mhz) g pgc+demodulator g out 67 64 59 -13 -16 -21 70 67 62 -10 -13 -18 73 70 65 -7 -10 -15 db db db db db db gmax; if = 246mhz gmax; if = 336mhz gmax; if = 435mhz gmin; if = 246mhz gmin; if = 336mhz gmin; if = 435mhz pgc: see table 4 page 11 and diagram 5.1, page 39 pgc controlled via 3 wire bus 1 1 63 pgc gain step gstep 2 db 1 64 i - q phase deviation ?? iq 3 deg see design hint 8.2, page 36 design hint 8.4, page 38 1 65 amplitude mismatch ? v(i/q) ? vi/q 1.7 db 1
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 22 22.03.00 ac/dc characteristics (cont'd) supply voltage v s = 2.7v to 4.5v; ambient temperature t a = 25c # parameter symbol limit values unit test condition test min. typ. max. circuit 3 wire bus inputs sygcdt/sygccl/pgcstr 66 input voltage l v l 00.5v 1 67 input voltage h v h 2.0 vs v 1 68 reference voltage vcomp 1.75 v 1/1.2 69 input current -i in 5 a 0v<=v in <=vs 1 70 clock frequency fsygccl 3.25 13 mhz 1/1.2 71 set - up time (start) tsusta 30 ns 1/1.2 72 h pulse width (clock) thigh 20 ns 1/1.2 73 l pulse width (clock) tlow 20 ns 1/1.2 74 set - up time ( data transfer ) tsudat 20 ns 1/1.2 75 hold time (data transfer ) thddat 20 ns 1/1.2 76 rise time tr 20 40 ns 1/1.2 77 fall time tf 20 35 ns 1/1.2 78 set - up time ( stop ) tsusto 30 ns 1/1.2 79 setting time t set 200 ns setting of gain after programming 1 80 start time t start 200 ns programming start time after power up 1 power-down and control inputs rxon1, rxon2, puplo2,oce 81 input voltage l v l 00.5v 1 82 input voltage h v h 2.0 vs v 1 83 input current l i l 2.5 a 0<=v pdl <=0.5v 1 84 input current h i h 25 a 2.0v<=v pdh <=vs 1 85 input capacitance c in 2pf
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 23 22.03.00 ac/dc characteristics (cont'd) supply voltage v s = 2.7v to 4.5v; ambient temperature t a = 25c # parameter symbol limit values unit test condition test min. typ. max. circuit differential operational amplifier (open loop) 86 slew rate sr 2.6 v/s 87 gain-bandwidth prod. gbw 12 mhz 88 voltage gain a vo 60 db 89 phase margin 60 degr. 90 gain margin a r 14 db 91 common-mode rejection cmr 70 db 92 offset voltage v off 1 mv at input inq/x,ini/x 93 output voltage (ir/x,qr/x) v out 2.5 vpp differential 94 diff. output offset volt.(ir/x,qr/x) v out/x 1 mv/ms with offset compensation ( s&h ) over the whole temperature range 1 95 dc output level (ir/x,qr/x) v outdc 0.95 v depends on so-dc output level 1 96 output resistor r(out/outx) 250 ? differential note: the operational amplifiers do not offer wideband capability (see also design hint 8.3 page 37 and design hint 8.4 page 38).
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 24 22.03.00 ac/dc characteristics (cont'd) supply voltage v s = 2.7v to 4.5v; ambient temperature t a = 25c # parameter symbol limit values unit test condition test min. typ. max. circuit sample and hold 97 voltage drift at output ir/x, qr/x v dritt 1 mv/ms ( csh1/2 = 47nf ) during hold time, dep. of capac. c, for the whole temperature range, see diagram 7, page 41 1 98 min. sample time t sample 50 350 s s csh1/2 120nf t pd2 off 10ms csh1/2 120nf t pd2 off 10ms see diagram 8, page 41 1 99 diff. output offset volt. at op-output v opdiff 5 mv during sample time and the beginning of hold time 1 100 diff. load at op-out single ended load to gnd single ended load to v ref rl diff rl se rl se 10 50 50 k ? m ? k ? 0.8v v ref 1.3v see diagram 8, page 41 note: the operational amplifiers do not offer wideband capability. in wideband applications,the sample and hold therefore must be deactivated by setting the oce input to l (see also design hint 8.4 page 38).
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 25 22.03.00 7 test circuits 7.1 test circuit 1 note: resistors r2 - r7, r8 - r13 and capacitors c27 - c31 are not necessary in a wideband application (see also design hint 8.4). however, the test board offers the possibility to mount these components (e.g. for a low pass filter in small band applications).
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 26 22.03.00 7.2 test circuit 1.1 (vco as oscillator) r201 r200 c201 c200 l4 c204 c203 c202 r203 r202 d2 7.3 test circuit 1.2 (3-wire-bus timing) tsusta set - up time ( start ) thigh h pulse width ( clock ) tlow l pulse width ( clock ) tsudat set - up time ( data transfer ) thddat hold time (data transfer ) tr rise time tf fall time tsusto set - up time ( stop ) rise and fall time to 20% and 80% values all other times referenced to vcomp
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 27 22.03.00 7.4 test circuit 2 7.4.1 test circuit 2a 7.4.2 test circuit 2b 7.4.3 test circuit 2c the s parameters are tested at the indicated frequency and the equivalent parallel or series circuit can be calculated on this base. test point test circuit test frequency / mhz pin x pin y lo1-input impedance 2a 200....2000 17 18 si-input impedance 2a 200....2000 13 14 mo-output impedance 2c 10.....600 20 21 ifi-input impedance 2a 10....600 8 9 lo2-input impedance 2a 10... 1000 32 35 lna-i/o impedance 2b 200 2000 29 26
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 28 22.03.00 7.5 test board (test boards pmb2407 v1.1 are available on request, also usable for pmb2408 v1.1) 7.5.1 test board: layout top
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 29 22.03.00 7.5.2 test board: layout bottom
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 30 22.03.00 7.5.3 test board: top place for test circuit 1
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 31 22.03.00 7.5.4 test board: bottom place for test circuit 1
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 32 22.03.00 7.5.5 test board: top place for test circuit 1.1
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 33 22.03.00 7.5.6 test board: bottom place for test circuit 1.1
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 34 22.03.00 7.5.7 list of components: test circuit 1 component values c1, c14 10nf c3, c4 47nf c2, c5, c8, c9, c10, c13, c24, c25 10pf c6, c7, c11, c12, c17, c18, c21, c22, c33, c34, c35, c100, c101 1nf c15, c32 1.8pf (if = 246mhz) c16 2.7pf (if = 246mhz) csi (not placed on test board, but it is possible to add the comp.) 2.2pf c26, c28, c29, c31 not required l5, l6 33nh (if = 246mhz) l8 330nh (lo2o = 164mhz) 47nh (lo2o = 492mhz) r100 51 r103 270 bal1, bal2, bal3, bal5 1:1 balun toko 617db-1023 bal4 1:2 balun toko 617db-1010 d2 bby51 test circuit 1.1 ( + components of test circuit 1 ) r200, r201 4.7k r202, r203 560 c200, c201 18p c202, c204 2.2p c203, c205 8.2p ( c203 and c205 are on test board as c203 differential between lo2e and lo2ex, a splitting of these capacitance are better for phase noise. it can be placed parallel to r202 and r203. ) l4 15n (492mhz) these components replace the following components of test circuit 1: bal5, r100, c100, c101, r103
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 35 22.03.00 8 design hints 8.1 lna matching for 925mhz ( gsm 900 ); all parameters are measured; dimensions in mm test boards are available matching circuit gain and nois figure results versus rf-frequency 19,5 20 20,5 21 21,5 22 22,5 875 885 895 905 915 925 935 945 955 965 975 1,2 1,4 1,6 1,8 2 2,2 2,4 gain nf (meas) nf (corr) gain/db; nf/db; f/mhz test board stability factor k > 2.3 input return loss > 17 db output return loss > 14 db
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 36 22.03.00 8.2 vco: possibility of i/q phase error correction with a wanted resistor mismatch in the external vco-circuit ( r202, r203 ) vco - test circuit r201 r200 c201 c200 l4 c204 c203 c202 r203 r202 d2 phase error correction diagram pvcodiff r202 = 1.00*r203 r202 ~ 1.20*r203 r202 ~ 1.45*r203 r202 ~ 1.75*r203 phase i/q to optimize phase-error the resistor r203 has to be fix and the resitor r202 has to be changed for the ideal phase. an increase of even harmonics of maximal 5db at lo2o/x-output can be expected. for example the vco has a diff. level of about -12.5dbm, r203=560 ? then r202 has to be 820 ? .
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 37 22.03.00 8.3 sample and hold: offset compensation diagram for smallband applications baseband frequency 400khz a differential dc-offset at the demodulator?s outputs is also amplified by the opamp?s. hence this differential offset must be compensated, it is sensed via the sample and hold circuitry (one separate circuit for each channel i and q) at both opamp?s outputs ir/irx (qr/qrx). a feedback loop corrects the remaining offset error below the tolerable input value of the baseband a/d converter. figure 8.3.1 shows the block diagram of one of the two offset compensation circuits. figure 8.3.2 shows the timing diagram of the compensation. the voltage drift during hold time is determined by the external capacitance c. figure 8.3.1: offset compensation diagram sec. mixer diff. op. amp. ic pmb2408 dc-coupling baseband codec + - vref iix i ix rrx oce c s vc v soix/ soqx soi/ soq inix/ inqx ini/ inq irx/ qrx ir/ qr csh figure 8.3.2: offset compensation timing t sample oce-input offset-voltage at diff. opamp-output voltage drift sample time hold time oce-input t rxon2 off rxon2 gnd
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 38 22.03.00 8.4 sample and hold: offset compensation diagram for wideband applications baseband frequency 400khz sec. mixer diff. op. amp. ic pmb2408 dc-coupling baseband codec + - vref iix i ix rrx oce s vc v soix/ soqx soi/ soq inix/ inqx ini/ inq irx/ qrx ir/ qr csh in wideband applications the use of the sample and hold is not to be recommended. the sample and hold has to be deactivated by connecting the pins csh1, csh2 and oce to gnd. explanation: the internal operational amplifiers do not offer wideband capability and will not be used in a wideband application. an offset compensation loop as described under 8.3 might cause an additional i/q phase error in the baseband path. (the operation point of the sample and hold circuitry has an influence on the roll-off of the i/q demodulator. since this operation point might be different between i and q channel, the baseband roll-off is also slightly different between i and q which causes an additional phase error). connecting the pins csh1, csh2 and oce to gnd avoids this problem and sets both sample and hold circuits in a defined state. note that this causes a differential output voltage of 100mv max. at the pins soi/soix (and soq/soqx, respectively).
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 39 22.03.00 9 diagrams 9.1 diagram 1: first mixer: output power 9.2 diagram 2: first mixer: noise figure nf versus lo-level p lo1, if = 246mhz versus lo-frequency f lo1 , if = 246mhz 9.3 diagram 3: first mixer: mixer gain 9.4 diagram 4: first mixer: noise figure nf versus lo-level p lo1, if = 246mhz versus lo-level p lo1 , if = 246mhz 9.5.1 diagram 5.1: gain, noise figure, 1db compression point and iicp3 of pgc versus prog. gain -12 -6 0 6 12 18 24 30 36 42 48 54 60 66 72 78 70 66 62 58 54 50 46 42 38 34 30 26 22 18 14 10 6 2 -2 -6 -10 gain (programmable)/db gain and noise figure /db -74 -69,2 -64,4 -59,6 -54,8 -50 -45,2 -40,4 -35,6 -30,8 -26 -21,2 -16,4 -11,6 -6,8 -2 1db compression point (input) / dbm iicp3 /dbm gain actual /db nf/db 1db compression point (input)/dbm iicp3/dbm
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 40 22.03.00 9.5.2 diagram 5.2: deviation from ideal gain versus prog. gain (parameter: temperature) typical gain characteristic of the pgc (parameter: temperature) -5 -4 -3 -2 -1 0 1 2 3 4 5 70 66 62 58 54 50 46 42 38 34 30 26 22 18 14 10 6 2 -2 -6 -10 gain (programmable) / db deviation from ideal gain (f_if = 250mhz) / db -30c 22c 80c 9.5.3 diagram 5.3: deviation / tolerances from typical pgc gain characteristic (fix-point: gain = 42db, temperature range: -20 - 80c) -2 -1,8 -1,6 -1,4 -1,2 -1 -0,8 -0,6 -0,4 -0,2 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 -10 0 10 20 30 40 50 60 70 gain (programmable) / db deviation / db
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 41 22.03.00 9.6 diagram 6: baseband frequency response versus baseband frequency (normalised to 1khz) -80 -70 -60 -50 -40 -30 -20 -10 0 10 1 khz 10 khz 100 khz 1 mhz 10 mhz 100 mhz 1 ghz fso gain deviation (normalised to 1khz) / db 2,7 v 4,5 v 9.7 diagram 7: sample and hold circuit: voltage drift (during hold time) versus capacitance c. 9.8 diagram 8: sample and hold circuit:maximum sample-time versus pd2 time in switched off mode. t rxon2 off csh1/2 <= 120nf load at op-output qr/qrx, ir/irx: diff. load rdiff >= 50kohm, single ended load rse to gnd rse >= 50 mohm diff. load rdiff >= 50kohm, single ended load rse to vref = 0.8 to 1.3v rse >= 50 kohm
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 42 22.03.00 9.9 diagram 9: s - parameters s - parameters are available on 3.5"-disk or by e-mail all s-parameters are measured. diagram 9.1: s parameters low noise amplifier lna (high - gain) f s11 s21 s12 s22 ghz mag ang mag ang mag ang mag ang 0.50000 0.60219 -40.3 10.69917 123.2 0.003164 117.3 0.94803 -11.0 0.60000 0.55175 -46.6 9.61832 114.8 0.004373 131.2 0.94778 -12.9 0.70000 0.49605 -48.1 8.75558 108.1 0.007302 125.5 0.93671 -14.8 0.80000 0.47690 -51.1 7.90483 102.5 0.009100 119.0 0.94320 -17.0 0.90000 0.43958 -55.5 7.26950 96.7 0.010875 112.7 0.92531 -19.0 1.00000 0.42526 -56.4 6.51932 91.7 0.013142 120.0 0.93766 -21.5 1.10000 0.42963 -58.4 5.87501 88.4 0.015218 117.5 0.94495 -23.9 1.20000 0.44745 -62.3 5.35753 86.9 0.016878 109.5 0.95041 -27.0 1.30000 0.47224 -69.4 5.07177 86.8 0.017269 104.7 0.95011 -30.4 1.40000 0.48599 -79.3 5.02650 86.8 0.016418 105.7 0.93809 -33.8 1.50000 0.47538 -91.1 5.17023 84.5 0.015493 118.0 0.91518 -36.6 1.60000 0.43460 -103.3 5.30013 79.3 0.019177 134.6 0.89318 -38.1 1.70000 0.37255 -112.9 5.26928 73.1 0.026538 138.2 0.88071 -38.8 1.80000 0.30599 -119.5 5.11285 66.9 0.038264 134.6 0.85575 -40.2 1.90000 0.24813 -122.2 4.88020 61.0 0.044188 127.0 0.90822 -40.8 2.00000 0.20416 -120.1 4.61071 56.2 0.051163 118.4 0.93424 -42.6 2.10000 0.17949 -114.5 4.35266 52.1 0.055754 110.0 0.95955 -45.3 2.20000 0.17545 -108.6 4.10839 48.4 0.059411 102.1 0.97890 -48.4 2.30000 0.18662 -104.2 3.87209 45.7 0.062352 94.8 1.00177 -52.3 2.40000 0.22967 -106.3 3.65636 44.5 0.059714 85.3 1.01585 -57.4 2.50000 0.27790 -116.7 3.61054 44.2 0.053020 78.8 1.01013 -63.5 s11, s22 = f ( f ) ( high - gain ) s21, s12 = f ( f ) ( high - gain ) f 2.0 1.2 1.8 0.6 0.9 50 25 10 0 100 +j50 +j20 +j10 -j10 -j25 -j50 -j100 -j250 +j100 +j250 250 2.5 0.9 0.6 1.2 1.8 2.0 2.5 s22 s11 90 0.04 0.08 4 8 45 0 -45 -90 -135 180 135 |s12| |s21| 2.5 1.8 1.2 0.6 0.9 2.0 s21 0.6 0.9 1.2 1.8 2.0 2.5 s12
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 43 22.03.00 noise parameters freq. nfmin opt yopt rn [ ghz ] [ db ] mag angle gopt [ms] bopt [ms] [ ? ] 0.9 1.386 0.201 23.2 13.62 -2.25 12.35 1.8 2.573 0.101 16.9 16.46 -0.97 18.45 noise characteristic 900mhz 1.8ghz f 50 25 10 0 100 +j50 +j20 +j10 -j10 -j25 -j50 -j100 -j250 +j100 +j250 250 1.38 1.5 1.6 1.8 2.0 2.5 f 50 25 10 0 100 +j50 +j20 +j10 -j10 -j25 -j50 -j100 -j250 +j100 +j25 0 250 2.57 2.7 2.8 3.0 3.5 4.0 diagram 9.2: s parameters low noise amplifier lna ( low - gain ) f s11 s21 s12 s22 ghz mag ang mag ang mag ang mag ang 0.50000 0.53673 -28.4 1.19991 119.7 0.004303 110.4 0.98268 -12.0 0.60000 0.55460 -36.2 1.04425 108.4 0.004681 125.0 0.97743 -14.5 0.70000 0.55834 -32.6 0.95402 100.1 0.008020 109.9 0.97039 -17.3 0.80000 0.60876 -40.3 0.82273 91.2 0.009226 104.0 0.96565 -20.0 0.90000 0.62694 -50.2 0.68876 84.9 0.008710 102.6 0.95902 -22.9 1.00000 0.66372 -58.3 0.57105 79.1 0.008306 103.7 0.95351 -25.8 1.10000 0.71236 -69.2 0.46408 77.3 0.008386 108.9 0.94672 -28.7 1.20000 0.73322 -82.7 0.37931 80.4 0.008422 132.1 0.93941 -31.7 1.30000 0.73998 -96.7 0.33736 88.4 0.011434 152.9 0.93136 -34.7 1.40000 0.72803 -111.4 0.33704 96.8 0.018059 160.8 0.92316 -37.7 1.50000 0.70182 -126.8 0.36716 101.3 0.026780 157.7 0.91338 -40.6 1.60000 0.66266 -142.7 0.40793 101.3 0.036729 151.0 0.90417 -43.3 1.70000 0.60969 -159.9 0.44921 98.2 0.047852 140.7 0.89373 -46.0 1.80000 0.54159 -178.4 0.48287 92.7 0.058903 129.9 0.88457 -48.6 1.90000 0.46230 162.3 0.49895 86.0 0.067609 118.6 0.87869 -51.2 2.00000 0.37371 142.1 0.49917 78.7 0.074069 106.8 0.86960 -53.6 2.10000 0.29255 123.9 0.48430 72.5 0.075587 95.4 0.86348 -56.3 2.20000 0.23181 105.7 0.46296 67.2 0.075901 86.4 0.85450 -59.4 2.30000 0.18204 84.7 0.44123 62.5 0.075077 77.9 0.84529 -62.7 2.40000 0.12474 56.2 0.41188 59.1 0.070290 68.1 0.83477 -66.6 2.50000 0.06166 15.7 0.38682 57.5 0.059321 62.8 0.82243 -70.9
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 44 22.03.00 s11, s22 = f ( f ) ( low - gain ) s21, s12 = f ( f ) ( low - gain ) 2ghz 0.9 0.6 50 25 10 0 100 +j50 +j20 +j10 -j10 -j25 -j50 -j100 -j250 +j100 +j250 250 1.2 1.8 2.0 2.5 1.4 s11 0.6 0.9 1.2 1.8 2.0 2.5 s22 90 0.04 0.08 0.4 0.8 45 0 -45 -90 -135 180 135 |s12| |s21| 2.5 0.9 1.2 2.0 1.8 0.6 s21 s12 0.6 0.9 1.2 1.8 2.5 2.0 diagram 9.3: s parameters first mixer signal input si/six f s11 s21 s12 s22 ghz mag ang mag ang mag ang mag ang
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 45 22.03.00 diagram 9.4: s parameters first mixer local oscillator input lo1/lo1x f s11 s21 s12 s22 ghz mag ang mag ang mag ang mag ang
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 46 22.03.00 diagram 9.5: s parameters first mixer output mo/mox f s11 s21 s12 s22 ghz mag ang mag ang mag ang mag ang
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 47 22.03.00 diagram 9.6: s parameters pgc if signal input ifi/ifix f s11 s21 s12 s22 ghz mag ang mag ang mag ang mag ang
pmb 2408 v1.1 the reproduction, transmission or use of this document is not permitted without expresswritten authority. offenders will be lia ble for damages. all rights, including rights created by patent grant or registration of a utility model or design, are reserved . infineon technologies ag 48 22.03.00 diagram 9.7: s parameters vco ( as amplifier ) second local oscillator input lo2/lo2x f s11 s21 s12 s22 ghz mag ang mag ang mag ang mag ang

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